Two weeks before the IDF, Intel and AMD give us some new details about the next CPU generation. Some facts was already know, like that the new Xeon-CPU (which will be compatible to the Xeon-MP Tigerton) will have six Penryn cores with a 16MByte L3-Cache and so about 1.9 Billion transistors on one die. Really new is the information is that the new AMD CPU Nehalem which should launch in the 3 quarter of 2008, will have only a256KByte Cache per core and so only a half of the Barcelone and Phenom core but with a L3 Cache of 8MByte. But there should be also some CPU´s with only 6MB L3 Cache. So we will see if Intel and AMD will be able to realize their promises.
3/18/2008
Subscribe to:
Post Comments (Atom)



0 COMMENTS:
Post a Comment